Seoul [South Korea], September 1 (ANI): Samsung Electronics unveiled its next-generation memory strategy at Semicon Taiwan, banking on 3D architectures to enhance capacity, bandwidth, and energy efficiency amid mounting artificial intelligence workloads, according to a news report by The Korea Herald.
Choi Jang-seok, head of the memory product planning team at Samsung Electronics, presented the road map during a keynote speech at the Memory Executive Summit in Taipei. The company designated the strategy “CUBE,” an acronym for capacity, utilization, bandwidth, and efficiency. Central to this approach is a transition toward vertically integrated structures designed to expand capacity without occupying additional board space.
“We will no longer be constrained by the printed circuit board area,” the news report quoted Choi.
“By expanding vertically, we can increase memory capacity without increasing the board footprint,” he added.
The company focused on optimizing the arrangement of logic and memory within 3D configurations to curb processing delays and accelerate data-transfer speeds through shorter die connections.
“3D is not simply about stacking. The key is how each layer is utilized,” Choi said.
“By dramatically shortening the distance between dies, we can create a vertical highway and substantially improve bandwidth,” he noted.
Addressing power consumption and heat generation in artificial intelligence systems remained another priority under the framework.
“The ultimate goal of 3D is to reduce the energy required to move a single bit of data,” Choi said.
The architecture extends the company’s high-bandwidth memory development beyond existing generations. Samsung undertook development of its eighth-generation HBM, designated HBM5, aiming for twice the performance of HBM4E, 20 per cent higher performance per watt, and 20 per cent lower thermal resistance.
Alongside HBM5, the company pursued zHBM, targeting eight times the performance of HBM4E, three times the performance per watt, and a reduction in thermal resistance between 75 and 90 per cent.
As per the news report, for high-capacity storage requirements in large language models, Samsung designed a NAND flash solution titled zNAND-O. The product aimed for 10 times the bit density of DRAM alongside seven times the read bandwidth and power efficiency of conventional NAND, with customer sampling targeted for 2028.
The product road map arrived as the firm maintained leadership positions in the global semiconductor landscape. Citing market tracker Counterpoint Research, the news report noted that Samsung’s second-quarter DRAM revenue share at 39 per cent, outpacing SK hynix at 26 per cent and Micron Technology at 25 per cent.
Samsung stated it intended to deploy its manufacturing scale and technology base across standard memory categories and high-value artificial intelligence lines. (ANI)
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